The invention pertains to electron emission devices. In particular applications, the invention pertains to methods of forming and utilizing buffer layers between resistive materials and conductive lines for field emission display devices.
Electron emission devices include display devices wherein electrons are emitted from cathode emitter tips toward phosphor molecules (the phosphor molecules can also be referred to herein as simply xe2x80x9cphosphorxe2x80x9d). An exemplary display device is a Field Emission Display (FED) device, such as the prior art FED device 10 described with reference to FIG. 1. Device 10 comprises a baseplate assembly 12 and a faceplate assembly 14.
Baseplate assembly 12 includes a substrate 16, column interconnects 18, a buffer layer 19, a resistor layer 20, electron emission tips 22, an extraction grid 24 and a dielectric layer 26.
Substrate 16 is preferably formed of an insulative glass material, and can be referred to as a baseplate. Column interconnects 18 are patterned over substrate 16. Column interconnects 18 comprise a conductive material, such as, for example, a metal. In preferred applications, column interconnects comprise an assembly of three sub-layers, with the sub-layers being an aluminum layer elevationally between a pair of chromium layers.
Buffer layer 19 is formed over column interconnects 18, and resistor layer 20 is formed over buffer layer 19. Buffer layer 19 comprises amorphous silicone and resistor layer 20 comprises conductively-doped amorphous silicon (preferably, boron-doped amorphous silicon).
Electron emission tips 22 are formed over substrate 16 at sites from which electrons are to be emitted, and can be constructed from conductively doped amorphous silicon. Emission tips 22 can have a number of pointed geometries, including, for example, pyramids and cones.
Extraction grid 24 (also referred to as a gate), is formed proximate emitter tips 22, and separated from substrate 16 with dielectric layer 26. Extraction grid 24 comprises a conductive material, such as, for example, conductively doped polysilicon. Extraction grid 24 is patterned to have openings 28 extending therethrough to expose electron emission tips 22. Dielectric layer 26 electrically insulates extraction grid 24 from electron emission tips 22, and the associated column interconnects 18.
Faceplate assembly 14 of FED device 10 is provided in a spaced relation relative to baseplate assembly 12, and is held in such spaced relation by insulative spacers 38.
Faceplate assembly 14 comprises a transparent substrate 36, and a transparent anode 34 formed proximate substrate 36. Substrate 36 can be referred to as a faceplate. Anode 34 can comprise, for example, indium tin oxide, and substrate 36 can comprise, for example, glass.
Faceplate assembly 14 comprises phosphor 32 supported by substrate 36 and defining pixels. Phosphor 32 comprises a luminescent material that generates visible light upon being excited by electrons emitted from electron emission tips 22. Phosphor 32 can comprise, for example, red/green/blue phosphor triads.
A voltage source 30 is provided to generate an operating voltage differential between electron emission tips 22, grid structure 24, and anode 34. One or more of emitter tips 22 can then be electrically stimulated to cause electrons 40 to be emitted toward phosphor 32. The impact of electrons 40 with phosphor 32 causes luminescence of phosphor 32. A person looking through transparent substrate 36 can see such luminescence. Accordingly, electron emission from emitter tips 22 is converted to an image visible through faceplate assembly 14.
FIGS. 2 and 3 illustrate alternative views of the baseplate assembly 12 of FED device 10, and show that electron emission tips 22 are grouped into discrete emitter sets 42, with the bases of the electron emission tips in each set being electrically connected to a common conductive interconnect 18. Further, FIG. 3. shows that emitter sets 42 are configured into columns (labeled as C1 and C2), with the individual emitter sets 42 in each column being connected to a common electrical interconnection. FIG. 3 also shows that the extraction grid 24 is divided into grid structures 25, with each emitter set 42 being associated with a different grid structure than the other emitter sets 42. In the shown embodiment, grid structures 25 are portions of extraction grid 24 that lie over a corresponding emitter set 42 and have openings 28 formed therethrough. Grid structures 25 are arranged in rows (labeled R1-R3) in which the individual grid structures in each row are connected to a common electrical connection.
In referring to columns and rows above, the term xe2x80x9ccolumnsxe2x80x9d is used to describe an arrangement of electron emission tips, and the term xe2x80x9crowsxe2x80x9d is used to describe an arrangement of grid structures, as is a conventional use of such terms. However, it is to be understood that the terms can be reversed in particular applications.
The arrangement of the grid structures in rows R1-R3 and the emitter sets in columns C1 and C2 defines an x-y addressable array of grid-controlled emitter sets. The two terminals, comprising the electron emission tips 22 and the grid structures, of the three terminal cold cathode emitter structure (where the third terminal is anode 34 in faceplate assembly 14 of FIG. 1) are commonly connected along such columns and rows, respectively, by means of high-speed interconnects. In particular, column interconnects 18 are formed over substrate 16, and row interconnects 44 are formed over the grid structures.
In operation, a specific emitter set is selectively activated by producing a voltage differential between the specific emitter set and the associated grid structure. The voltage differential may be selectively established through corresponding drive circuitry that generates row and column signals that intersect at the location of the specific emitter set. Referring to FIG. 3, for example, a row signal along R2 of the extraction grid 24 and a column signal along C1 of emitter set 42 activates the emitter set at the intersection of row R2 and column C1. The voltage differential between the grid structure and the associated emitter set produces a localized electric field that causes emission of electrons from the activated emitter set.
Early field emission devices were assembled without resistor layer 20 and suffered from uneven emission between different electron emission tips 22, with the result that noticeably bright and dim spots were produced on the screens of the flat panel displays. The problem of uneven emission was significantly reduced by including resistor layer 20, shown in FIGS. 1 and 2, between column interconnects 18 and electron emission tips 22. Resistor layer 20 can act as a ballast against excessive current through electron emission tips 22, thereby making electron emission roughly uniform among different electron emission tips. Moreover, in the absence of resistor layer 20, short circuiting between column interconnects 18 and row interconnects 44 was sometimes observed.
Problems can, however, be associated with the resistor layer 20. For instance, resistor layer 20 is found to occasionally have xe2x80x9cpinholexe2x80x9d defects or other discontinuities, which can lead to breakdown of the resistor layer. Accordingly, buffer layer 19 was developed to be inserted between conductive interconnects 18 and resistor layer 20. Buffer layer 19 generally comprises undoped amorphous silicon, and is formed through plasma enhanced chemical vapor deposition (PECVD) of silane in an atmosphere having a temperature of less than 400xc2x0 C., a pressure in a range of from about 500 mTorr to about 1,200 mTorr, and an operating power in a range of from about 200 watts to about 500 watts. Most preferably, the PECVD is conducted at a temperature of less than about 350xc2x0 C. The silane can be introduced at a rate in a range of from about 500 standard cubic centimeters per minute (sccm) to about 800 sccm, and buffer layer 19 is preferably formed to a thickness in a range of from about 200 Angstroms to about 1,000 Angstroms, with a preferred thickness being from about 800 Angstroms to about 1,000 Angstroms.
Buffer layer 19 provides a protective Tayer between resistor layer 20 and conductive interconnect 18. For instance, if discontinuities (such as, for example, pinholes) are formed within resistor layer 20, such discontinuities will terminate on buffer layer 19, rather than extending to conductive interconnect 18. Buffer layer 19 can thus avoid shorting that would otherwise occur in the absence of buffer layer 19.
While buffer layer 19 alleviates many of the problems associated with prior art devices lacking buffer layer 19, problems have been found to occur in utilizing the above-described buffer layer 19. For instance, in preferred applications in which conductive layer 18 comprises a sandwich of chromium, aluminum and chromium sub-layers, it is found that the above-discussed buffer layer 19 can have poor adhesion to an outer chromium surface of the conductive interconnect 18. It would, therefore, be desirable to develop alternative buffer layers. It would also be desirable to develop methods for incorporating such alternative of buffer layers into electron emission devices, such as, for example, field emission display devices.
In one aspect, an electron emission device comprises a substrate, and a first layer supported by the substrate. The first layer comprises a conductive material. The electron emission display device further comprises an electron emission tip electrically connected with the first layer, and a second layer electrically disposed between the first layer and the electron emission tip. The second layer comprises microcrystalline silicon.
In another aspect, the invention encompasses a method of forming an electron emission device. A substrate is provided, and a conductive layer is formed over the substrate. A microcrystalline-silicon-containing layer is formed over the conductive layer, and a resistor layer is formed over the microcrystalline-silicon-containing layer. An emitter tip is formed over the resistor layer.
In yet other aspects, the invention encompasses field emission display devices, and methods of forming field emission display devices.